The present invention relates to clock generation systems, and more particularly to a digital video clock generation system for digital video systems that deal with both component and composite digital video standards.
Component video standards, such as those defined in Recommendation ITU-R BT.656 "Interfaces for Digital Component Video Signals in 525-line and 625-line Television Systems Operating at the 4:2:2 level of Recommendation 601", incorporated herein by reference, normally specify a data rate of 27 MHZ, while composite digital standards, such as SMPTE 244M and IEC 1709 Section 5, incorporated herein by reference, specify a data rate related to the systems color subcarrier frequency, i.e., four times the subcarrier frequency (4 fsc). For a system that deals with both data rates, such as digital composite to digital component transcoders, a 27 MHz and 4 fsc clock needs to be generated. The 4 fsc clock needs to be locked to the color burst of the video signal being used as a synchronization source, while the 27 MHz clock simultaneously needs to be locked to the horizontal line rate of the same video signal. In order to facilitate signal processing, i.e., sample rate conversion, the relationship between the 27 MHz clock, the 4 fsc clock and the video signal needs to be precisely known, i.e., the frequencies need to be precisely related. It also means that the phase relationship, as defined at a specific point on the synchronization source video signal, needs to be precisely known.
What is desired is a digital video clock generation system that achieves precise relationship between the 27 MHz clock, the 4 fsc clock and the synchronization source video signal in a reliable manner for both PAL and NTSC video systems with only minor changes in system overall operation.